1. Field of Invention
This invention relates generally to a semiconductor ROM, the Read-Only Memory. In particular, it relates to a ROM cell and its related sensing scheme for reading which can store multiple bits.
2. Description of Related Art
A semiconductor memory is typically comprised of an array of memory cells which are aligned in rows and columns as shown in FIG. 1. A memory cell 11 is used to store data for future use. For area efficiency, a memory array includes a large amount of memory cells 12. A word line, WL runs across top of hundreds or even thousands of memory cell gates which makes the WL capacitance load quite large and needs a big driver 7 to accelerating the speed of charging up the capacitive load of memory cells hooked to the same word line.
The Read Only Memory, ROM has advantages of small cell size and fully compatible standard CMOS logic process and therefore costs least price to manufacture compared to its counter parts other memories like SRAM, DRAM or some Non-Volatile Memories, NVM including flash or EPROM memories. A prior art ROM cell as shown in FIG. 1 is commonly comprised of an N-type device 1 with a fixed channel width and length. The gate of the ROM device is hooked to a world line 2 while another node of diffusion, so named as “drain” is hooked into a so named “bit line” 3 and the other node of diffusion is grounded to the return of power supply which in most likely grounded to “0V” in a standard CMOS process. In the mask design or layout of the ROM cell as shown in top right of FIG. 1, a contact 4 is used to connect drain of diffusion node to a bit line, a poly running across top of the thin oxide layer forms the gate of an ROM cell which is connected to the word line. For reliability of cell size, there will be minimum spacing between the contact and the edge 5 of diffusion area and the spacing between an edge of diffusion to the poly 6. Most ROM cell in CMOS process use a minimum channel length of NMOS device. The spacing between the contact and the edge of diffusion plus the shape of contact determines the area of an ROM cell. The prior art of an ROM cell with minimum size has empty area as shown in FIG. 1 layout diagram.
The prior art of the ROM design mainly is comprised of cell with a fixed channel width and length and a fixed threshold voltage. This limits the density of representing one bit for each ROM cell.